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Text of the page (random words):
meta title d central asic control board reference description reference for 12 bitcoin asic miner control boards the controller that drives the hashboards soc cpu models hashboard chip family pic vs no pic host interface and flash notes generated 2026 06 21t02 09 27 00 00 version 1 0 license https creativecommons org licenses by 4 0 license_name cc by 4 0 source https d central tech asic control board reference record_count 12 provenance d central mining bible antminer_architecture master_chip_catalog the laval asic repair bench disclaimer a reference control board revisions vary within a model line confirm the exact board markings soc nand connector before flashing or swapping a controller rows id zynq s9 gen board xilinx zynq controller s9 gen zynq7007 bmu prefix am1 s9 soc xilinx zynq 7010 xc7z010 xc7z007s variant with artix 7 fpga fabric cpu dual arm cortex a9 667 mhz zynq 7010 models s9 s9i s9j t9 s9d r4 chip_family bm1387 sha 256 pic pic pic16f1704 x3 at i2c 0x55 0x56 0x57 interface fpga uart fifos axi 0x43c00000 fpga axi iic 0x41600000 asic chain notes boots fsbl fpga bitstream u boot from 256mb nand or sd via j3 jumper the root ramdisk is only sha256 verified so a dcent_os image can replace it while reusing the stock boot chain building on community open tooling bible_source antminer_architecture md control board specs l32 90 i2c bus map l304 318 master_chip_catalog md 10 5 7 pic table id zynq s17 gen board xilinx zynq controller s17 t17 gen am2 s17 soc xilinx zynq 7000 class xc7z010 xc7z007s with fpga fabric cpu dual arm cortex a9 667 mhz zynq 7010 class models s17 s17 t17 t17 chip_family bm1397 sha 256 pic pic dspic33ep16gs202 interface fpga uart fifos axi asic chain notes same zynq boot chain as the s9 generation but with a 4 6 x kernel aftermarket os images typically replace only the nand ramdisk and reuse the stock fsbl fpga which eases a dcent_os port bible_source master_chip_catalog md 10 5 zynq am2 s17 bm1397 dspic33ep16gs202 id zynq s19 gen board xilinx zynq controller s19 t19 gen c55 c71 am2 soc xilinx zynq 7010 xc7z007s 010 with artix 7 fpga fabric cpu dual arm cortex a9 667 mhz zynq 7010 models s19 s19 pro s19a s19a pro early zynq c55 c71 boards chip_family bm1398 sha 256 pic pic dspic33ep16gs202 interface fpga uart fifos axi fpga i2c asic chain notes c55 c71 boards boot zynq fsbl fpga u boot from nand with an external sd recovery slot dcent_os targets them via the same sha256 only ramdisk replacement path used on the s9 gen board bible_source antminer_architecture md s19 system diagram l4 30 control_board_security md 8 2 c55 c71 xc7z007s 010 master_chip_catalog md 10 5 zynq am2 bm1398 id zynq l7 board xilinx zynq controller l7 scrypt xil l7 soc xilinx zynq 7000 class xc7z010 family exact part uncertain with fpga fabric cpu dual arm cortex a9 zynq 7000 class clock not separately stated models l7 l7 hydro scrypt chip_family bm1489 scrypt pic uncertain psu enable on gpio907 voltage controller type not identified interface fpga uart fifos axi asic chain notes scrypt class zynq controller whose init only sets psu enable gpio907 and leds with the hashboard chain brought up over fpga uart a dcent_os scrypt path would mirror the sha 256 uart driver model bible_source master_chip_catalog md 10 5 zynq xil l7 bm1489 wave6 mining b1 inits md 5 l7 gpio907 psu_en id beaglebone am335x board beaglebone style am335x controller bbctrl bb18 soc ti am335x sitara am3352 in the board table cpu single arm cortex a8 clock not stated in bible models l3 l3 scrypt late 2021 s19j s19j pro stock bb bb18 board chip_family bm1485 l3 scrypt bm1398 bm1362 s19j era stock bb pic pic present l3 pic mac pairing dspic33ep on s19j era stock bb interface software uart dev ttyo1 2 4 linux i2c no fpga notes no fpga and no kernel modules asic chains are driven over standard linux uarts making this the simplest dcent_os target boots mlo u boot kernel ramdisk from nand or an internal sd card bible_source antminer_architecture md beaglebone l92 105 wave6 mining b1 inits md 3 l3 bbb gpio map id cvitek cv1835 board cvitek cv1835 controller cvctrl c88 cb8 cb4 soc cvitek sophgo cv1835 cv183x family cpu dual arm cortex a53 1 0 ghz armv8 a runs aarch32 under stock firmware models s19k pro s19 xp s19j pro s19j xp s21 t21 ks3 ks5 x5 l9 c88 cb8 cb4 boards chip_family bm1362 bm1366 bm1368 s21 bm1489 l9 pic pic dspic33ep interface uart stock uart_trans ko or userspace software uart linux i2c no fpga notes boots an atf fip chain fsbl opensbi u boot from spi nand with secure boot third party os images commonly run as a reboot non persistent overlay so a clean dcent_os install needs network re injection or a board with the external sd slot bible_source control_board_security md 1 3 cv1835 arch 8 2 board table master_chip_catalog md 10 5 cvitek cv1835 bm1362 bm1366 id amlogic axg board amlogic axg controller amlctrl am3 aml c76 c81 c83 cbe soc amlogic a113d axg soc family cpu quad core arm cortex a53 1 2 ghz armv8 a arm64 kernel armhf userspace models s19j pro s19 xp s19k pro s21 s21 pro s21 xp s21 l9 c76 c81 c83 cbe boards chip_family bm1362 bm1366 bm1368 bm1370 bm1489 l9 pic pic dspic33ep on s19j era boards no pic on s21 generation tas5782m dac drives vid interface software uart dev ttys1 4 linux i2c no fpga notes quad a53 axg with secure boot from spi nand and micro usb otg recovery firmware blocked on units shipped sept 2025 s21 gen boards drop the pic consistent with the chip canon and share a common power on init across the s21 family bible_source antminer_architecture md amlogic l107 136 control_board_security md 4 a113d 8 2 c76 c81 c83 cbe master_chip_catalog md 7 nopic tas5782m 10 5 aml id esp32 s3 bitaxe board esp32 s3 self contained controller bitaxe class open hardware soc espressif esp32 s3 cpu espressif esp32 s3 microcontroller models bitaxe ultra hex supra bm1366 bitsupra bm1368 bitaxe gamma bm1370 bitaxe touch bm1370 planned and similar open single board miners chip_family bm1366 bm1368 bm1370 single chip pic no pic tps546 buck regulator single asic interface uart i2c direct to a single asic notes self contained open hardware controller driving one asic over uart i2c with a tps546 buck regulator firmware is flashed directly over usb making it the most accessible dcent class target and the spirit of building on prior open work bible_source master_chip_catalog md 6 esp32 s3 bitaxe 10 5 tps546 gamma bm1370 per 15 bible docs catalog l96 225 is the isolated error id allwinner whatsminer board allwinner h series controller whatsminer microbt h3 h6 h616 soc allwinner h3 h6 h616 cpu allwinner h3 h6 h616 cores not detailed in bible models whatsminer m1 m3 m8 m12 m19 m20s m50 m60s d series microbt chip_family microbt k series k1 k2 k3 d not bitmain bm pic no pic uart command byte voltage control interface uart command byte protocol per model profile from eeprom chip_id via uci notes openwrt procd controller where cgminer selects a per model uci profile from the eeprom chip_id and drives the chain over a uart command byte protocol bible_source master_chip_catalog md 3 k series chip_id 10 5 allwinner h3 h6 h616 wave6 mining b3 inits md 11 12 id innosilicon armv7 board innosilicon armv7 controller t series soc custom innosilicon armv7 soc cpu custom innosilicon armv7 soc cores not detailed in bible models innosilicon t2tz dragonmint t1 heritage t series chip_family innosilicon t2t not bitmain bm pic uncertain mcompat hal pwm voltage backend not pic based interface uncertain mcompat hal pwm_soc_hub backend notes custom armv7 soc running a cgminer fork with an mcompat hardware abstraction layer for voltage pwm bible_source master_chip_catalog md 5 innosilicon t series gap c 10 5 wave6 mining b3 inits md 8 10 id k210 avalon board kendryte k210 controller avalon industrial bare metal soc kendryte k210 risc v cpu kendryte k210 risc v bare metal no linux init models avalon a1346 a14x a15x canaan industrial chip_family canaan avalon a3197s a3198s a3200c plus not bitmain bm pic uncertain voltage control encrypted in mm_miner firmware interface uncertain encrypted mm_miner k210 spi flash bootloader main loop notes bare metal risc v controller with no linux init the mm_miner image is aes cbc encrypted with the key in k210 otp efuse so the platform is effectively closed to custom firmware bible_source master_chip_catalog md 4 avalon chips gap a 10 5 k210 risc v wave6 mining b3 inits md 14 id k230 avalon board kendryte k230 linux controller avalon home class soc kendryte k230 risc v cpu kendryte k230 risc v runs linux models avalon nano 3 3s mini 3 canaan home class some fields uncertain chip_family canaan avalon home class chips uncertain not bitmain bm pic uncertain interface uncertain notes newer risc v controller that runs linux on canaan s home class miners incl the avalon mini 3 board and chip details still flagged tbd in the bible bible_source master_chip_catalog md 10 5 k230 risc v linux avalon home