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ore significant 67 68 these newer concerns are among the many factors causing researchers to investigate new methods of computing such as the quantum computer as well as to expand the use of parallelism and other methods that extend the usefulness of the classical von neumann model operation edit the fundamental operation of most cpus regardless of the physical form they take is to execute a sequence of stored instructions that is called a program the instructions to be executed are kept in some kind of computer memory nearly all cpus follow the fetch decode and execute steps in their operation which are collectively known as the instruction cycle after the execution of an instruction the entire process repeats with the next instruction cycle normally fetching the next in sequence instruction because of the incremented value in the program counter if a jump instruction was executed the program counter will be modified to contain the address of the instruction that was jumped to and program execution continues normally in more complex cpus multiple instructions can be fetched decoded and executed simultaneously this section describes what is generally referred to as the classic risc pipeline which is quite common among the simple cpus used in many electronic devices often called microcontrollers it largely ignores the important role of cpu cache and therefore the access stage of the pipeline some instructions manipulate the program counter rather than producing result data directly such instructions are generally called jumps and facilitate program behavior like loops conditional program execution through the use of a conditional jump and existence of functions c in some processors some other instructions change the state of bits in a flags register these flags can be used to influence how a program behaves since they often indicate the outcome of various operations for example in such processors a compare instruction evaluates two values and sets or clears bits in the flags register to indicate which one is greater or whether they are equal one of these flags could then be used by a later jump instruction to determine program flow fetch edit fetch involves retrieving an instruction which is represented by a number or sequence of numbers from program memory the instruction s location address in program memory is determined by the program counter pc called the instruction pointer in intel x86 microprocessors which stores a number that identifies the address of the next instruction to be fetched after an instruction is fetched the pc is incremented by the length of the instruction so that it will contain the address of the next instruction in the sequence d often the instruction to be fetched must be retrieved from relatively slow memory causing the cpu to stall while waiting for the instruction to be returned this issue is largely addressed in modern processors by caches and pipeline architectures see below decode edit further information instruction set architecture instruction encoding the instruction that the cpu fetches from memory determines what the cpu will do in the decode step performed by binary decoder circuitry known as the instruction decoder the instruction is converted into signals that control other parts of the cpu the way in which the instruction is interpreted is defined by the cpu s instruction set architecture isa e often one group of bits that is a field within the instruction called the opcode indicates which operation is to be performed while the remaining fields usually provide supplemental information required for the operation such as the operands those operands may be specified as a constant value called an immediate value or as the location of a value that may be a processor register or a memory address as determined by some addressing mode in some cpu designs the instruction decoder is implemented as a hardwired unchangeable binary decoder circuit in others a microprogram is used to translate instructions into sets of cpu configuration signals that are applied sequentially over multiple clock pulses in some cases the memory that stores the microprogram is rewritable making it possible to change the way in which the cpu decodes instructions execute edit after the fetch and decode steps the execute step is performed depending on the cpu architecture this may consist of a single action or a sequence of actions during each action control signals electrically enable or disable various parts of the cpu so they can perform all or part of the desired operation the action is then completed typically in response to a clock pulse very often the results are written to an internal cpu register for quick access by subsequent instructions in other cases results may be written to slower but less expensive and higher capacity main memory for example if an instruction that performs addition is to be executed registers containing operands numbers to be summed are activated as are the parts of the arithmetic logic unit alu that perform addition when the clock pulse occurs the operands flow from the source registers into the alu and the sum appears at its output on subsequent clock pulses other components are enabled and disabled to move the output the sum of the operation to storage e g a register or memory if the resulting sum is too large i e it is larger than the alu s output word size an arithmetic overflow flag will be set influencing the next operation structure and implementation edit see also processor design block diagram of a basic uniprocessor cpu computer black lines indicate data flow whereas red lines indicate control flow arrows indicate flow directions hardwired into a cpu s circuitry is a set of basic operations it can perform called an instruction set such operations may involve for example adding or subtracting two numbers comparing two numbers or jumping to a different part of a program each instruction is represented by a unique combination of bits known as the machine language opcode while processing an instruction the cpu decodes the opcode via a binary decoder into control signals which orchestrate the behavior of the cpu a complete machine language instruction consists of an opcode and in many cases additional bits that specify arguments for the operation for example the numbers to be summed in the case of an addition operation going up the complexity scale a machine language program is a collection of machine language instructions that the cpu executes the actual mathematical operation for each instruction is performed by a combinational logic circuit within the cpu s processor known as the arithmetic logic unit or alu in general a cpu executes an instruction by fetching it from memory using its alu to perform an operation and then storing the result to memory besides the instructions for integer mathematics and logic operations various other machine instructions exist such as those for loading data from memory and storing it back branching operations and mathematical operations on floating point numbers performed by the cpu s floating point unit fpu 69 control unit edit main article control unit the control unit cu is a component of the cpu that directs the operation of the processor it tells the computer s memory arithmetic and logic unit and input and output devices how to respond to the instructions that have been sent to the processor it directs the operation of the other units by providing timing and control signals most computer resources are managed by the cu it directs the flow of data between the cpu and the other devices john von neumann included the control unit as part of the von neumann architecture in modern computer designs the control unit is typically an internal part of the cpu with its overall role and operation unchanged since its introduction 70 arithmetic logic unit edit main article arithmetic logic unit symbolic representation of an alu and its input and output signals the arithmetic logic unit alu is a digital circuit within the processor that performs integer arithmetic and bitwise logic operations the inputs to the alu are the data words to be operated on called operands status information from previous operations and a code from the control unit indicating which operation to perform depending on the instruction being executed the operands may come from internal cpu registers external memory or constants generated by the alu itself when all input signals have settled and propagated through the alu circuitry the result of the performed operation appears at the alu s outputs the result consists of both a data word which may be stored in a register or memory and status information that is typically stored in a special internal cpu register reserved for this purpose modern cpus typically contain more than one alu to improve performance address generation unit edit main article address generation unit the address generation unit agu sometimes also called the address computation unit acu 71 is an execution unit inside the cpu that calculates addresses used by the cpu to access main memory by having address calculations handled by separate circuitry that operates in parallel with the rest of the cpu the number of cpu cycles required for executing various machine instructions can be reduced bringing performance improvements while performing various operations cpus need to calculate memory addresses required for fetching data from the memory for example in memory positions of array elements must be calculated before the cpu can fetch the data from actual memory locations those address generation calculations involve different integer arithmetic operations such as addition subtraction modulo operations or bit shifts often calculating a memory address involves more than one general purpose machine instruction which do not necessarily decode and execute quickly by incorporating an agu into a cpu design together with introducing specialized instructions that use the agu various address generation calculations can be offloaded from the rest of the cpu and can often be executed quickly in a single cpu cycle capabilities of an agu depend on a particular cpu and its architecture thus some agus implement and expose more address calculation operations while some also include more advanced specialized instructions that can operate on multiple operands at a time some cpu architectures include multiple agus so more than one address calculation operation can be executed simultaneously which brings further performance improvements due to the superscalar nature of advanced cpu designs for example intel incorporates multiple agus into its sandy bridge and haswell microarchitectures which increase bandwidth of the cpu memory subsystem by allowing multiple memory access instructions to be executed in parallel memory management unit mmu edit main article memory management unit many microprocessors in smartphones and desktop laptop server computers have a memory management unit mmu translating logical addresses into physical ram addresses providing memory protection and paging abilities useful for virtual memory the mmu is usually integrated in the processor but in some cases it is in a separate integrated circuit ic 72 simpler processors especially microcontrollers usually do not include an mmu cache edit a cpu cache is a memory used by the central processing unit cpu of a computer to reduce the average cost time or energy to access data from the main memory 73 a cache is a smaller faster memory closer to a processor core which stores copies of the data from frequently used main memory locations most cpus have different independent caches usually organized as a hierarchy of several cache levels l1 l2 l3 l4 etc each ascending cache level is typically slower but larger than the preceding level with l1 being the fastest and the closest to the cpu at the l1 level there are usually separate instruction and data caches most modern fast cpus with few specialized exceptions f have multiple levels of cpu caches the first cpus that used a cache had only one level of cache unlike later level 1 caches it was not split into l1d for data and l1i for instructions almost all current cpus with caches have a split l1 cache they also have l2 caches and for larger processors l3 caches as well the l2 cache is usually not split and acts as a common repository for the already split l1 cache every core of a multi core processor has a dedicated l2 cache and is usually not shared between the cores the l3 cache and higher level caches are shared between the cores and are not split an l4 cache is currently uncommon and is generally on dynamic random access memory dram rather than on static random access memory sram on a separate die or chip that was also the case historically with l1 while bigger chips have allowed integration of it and generally all cache levels with the possible exception of the last level each extra level of cache tends to be bigger and is optimized differently other types of caches exist that are not counted towards the cache size of the most important caches mentioned above such as the translation lookaside buffer tlb that is part of the memory management unit mmu that most cpus have caches are generally sized in powers of two 2 8 16 etc kib or mib for larger non l1 sizes although the ibm z13 has a 96 kib l1 instruction cache 74 clock rate edit main article clock rate most cpus are synchronous circuits which means they employ a clock signal to pace their sequential operations the clock signal is produced by an external oscillator circuit that generates a consistent number of pulses each second in the form of a periodic square wave the frequency of the clock pulses determines the rate at which a cpu executes instructions and consequently the faster the clock the more instructions the cpu will execute each second to ensure proper operation of the cpu the clock period is longer than the maximum time needed for all signals to propagate move through the cpu in setting the clock period to a value well above the worst case propagation delay it is possible to design the entire cpu and the way it moves data around the edges of the rising and falling clock signal this has the advantage of simplifying the cpu significantly both from a design perspective and a component count perspective however it also carries the disadvantage that the entire cpu must wait on its slowest elements even though some portions of it are much faster this limitation has largely been compensated for by various methods of increasing cpu parallelism see below however architectural improvements alone do not solve all of the drawbacks of globally synchronous cpus for example a clock signal is subject to the delays of any other electrical signal higher clock rates in increasingly complex cpus make it more difficult to keep the clock signal in phase synchronized throughout the entire unit this has led many modern cpus to requ...