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alized results of their work circulated around bell labs in the form of btl memos before being published in 1957 at shockley semiconductor shockley had circulated the preprint of their article in december 1956 to all his senior staff including jean hoerni 16 17 18 19 who would later invent the planar process in 1959 while at fairchild semiconductor 20 21 1957 diagram of one of the sio2 transistor devices made by frosch and derick 15 after this j r ligenza and w g spitzer studied the mechanism of thermally grown oxides fabricated a high quality si sio 2 stack and published their results in 1960 22 23 24 following this research mohamed atalla and dawon kahng proposed a silicon mos transistor in 1959 25 and successfully demonstrated a working mos device with their bell labs team in 1960 26 27 their team included e e labate and e i povilonis who fabricated the device m o thurston l a d asaro and j r ligenza who developed the diffusion processes and h k gummel and r lindner who characterized the device 28 29 this was a culmination of decades of field effect research that began with lilienfeld simulation of formation of inversion channel electron density and attainment of threshold voltage iv in a nanowire mosfet note threshold voltage for this device lies around 0 45 v the first mos transistor at bell labs was about 100 times slower than contemporary bipolar transistors and was initially seen as inferior nevertheless kahng pointed out several advantages of the device notably ease of fabrication and its application in integrated circuits composition photomicrograph of two metal gate mosfets in a test pattern probe pads for two gates and three source drain nodes are labeled silicon remains the primary semiconductor in cmos devices but to enhance carrier mobility manufacturers most notably ibm and intel induce strain in the silicon channel by incorporating silicon germanium sige in nearby regions or applying stress engineering techniques thereby improving transistor performance without using sige alloys as the channel material itself citation needed many semiconductors with better electrical properties than silicon such as gallium arsenide do not form good semiconductor to insulator interfaces and thus are not suitable for mosfets research continues on creating insulators with acceptable electrical characteristics on other semiconductor materials citation needed to overcome the increase in power consumption due to gate current leakage a high κ dielectric is used instead of silicon dioxide for the gate insulator while polysilicon is replaced by metal gates e g intel 2009 30 the gate is separated from the channel by a thin insulating layer traditionally of silicon dioxide and later of silicon oxynitride some companies use a high κ dielectric and metal gate combination in the 45 nanometer node when a voltage is applied between the gate and the source the electric field generated penetrates through the oxide and creates an inversion layer or channel at the semiconductor insulator interface the inversion layer provides a channel through which current can pass between source and drain terminals varying the voltage between the gate and body modulates the conductivity of this layer and thereby controls the current flow between drain and source this is known as enhancement mode operation metal oxide semiconductor structure on p type silicon metal oxide semiconductor structure the traditional metal oxide semiconductor mos structure is obtained by growing a layer of silicon dioxide sio 2 on top of a silicon substrate commonly by thermal oxidation and depositing a layer of metal or polycrystalline silicon the latter is commonly used as silicon dioxide is a dielectric material its structure is equivalent to a planar capacitor with one of the electrodes replaced by a semiconductor when a voltage is applied across a mos structure it modifies the distribution of charges in the semiconductor if we consider a p type semiconductor with n a the density of acceptors p the density of holes p n a in neutral bulk a positive voltage v g from gate to body see figure creates a depletion layer by forcing the positively charged holes away from the gate insulator semiconductor interface leaving exposed a carrier free region of immobile negatively charged acceptor ions see doping if v g is high enough a high concentration of negative charge carriers forms in an inversion layer located in a thin layer next to the interface between the semiconductor and the insulator conventionally the gate voltage at which the volume density of electrons in the inversion layer is the same as the volume density of holes in the body is called the threshold voltage when the voltage between transistor gate and source v g exceeds the threshold voltage v th the difference is known as overdrive voltage this structure with p type body is the basis of the n type mosfet which requires the addition of n type source and drain regions mos capacitors and band diagrams this section does not cite any sources please help improve this section by adding citations to reliable sources unsourced material may be challenged and removed january 2019 learn how and when to remove this message the mos capacitor structure is the heart of the mosfet consider a mos capacitor where the silicon base is of p type if a positive voltage is applied at the gate holes which are at the surface of the p type substrate will be repelled by the electric field generated by the voltage applied at first the holes will simply be repelled and what will remain on the surface will be immobile negative atoms of the acceptor type which creates a depletion region on the surface a hole is created by an acceptor atom e g boron which has one less electron than a silicon atom holes are not actually repelled being non entities electrons are attracted by the positive field and fill these holes this creates a depletion region where no charge carriers exist because the electron is now fixed onto the atom and immobile as the voltage at the gate increases there will be a point at which the surface above the depletion region will be converted from p type into n type as electrons from the bulk area will start to get attracted by the larger electric field this is known as inversion the threshold voltage at which this conversion happens is one of the most important parameters in a mosfet in the case of a p type mosfet bulk inversion happens when the intrinsic energy level at the surface becomes smaller than the fermi level at the surface this can be seen on a band diagram the fermi level defines the type of semiconductor in discussion if the fermi level is equal to the intrinsic level the semiconductor is of intrinsic or pure type if the fermi level lies closer to the conduction band valence band then the semiconductor type will be of n type p type when the gate voltage is increased in a positive sense for the given example clarification needed this will shift the intrinsic energy level band so that it will curve downwards towards the valence band if the fermi level lies closer to the valence band for p type there will be a point when the intrinsic level will start to cross the fermi level and when the voltage reaches the threshold voltage the intrinsic level does cross the fermi level and that is what is known as inversion at that point the surface of the semiconductor is inverted from p type into n type if the fermi level lies above the intrinsic level the semiconductor is of n type therefore at inversion when the intrinsic level reaches and crosses the fermi level which lies closer to the valence band the semiconductor type changes at the surface as dictated by the relative positions of the fermi and intrinsic energy levels structure and channel formation see also field effect semiconductor channel formation in nmos mosfet shown as band diagram top panels an applied gate voltage bends bands depleting holes from surface left the charge inducing the bending is balanced by a layer of negative acceptor ion charge right bottom panel a larger applied voltage further depletes holes but conduction band lowers enough in energy to populate a conducting channel c v profile for a bulk mosfet with different oxide thickness the leftmost part of the curve corresponds to accumulation the valley in the middle corresponds to depletion the curve on the right corresponds to inversion a mosfet is based on the modulation of charge concentration by a mos capacitance between a body electrode and a gate electrode located above the body and insulated from all other device regions by a gate dielectric layer if dielectrics other than an oxide are employed the device may be referred to as a metal insulator semiconductor fet misfet compared to the mos capacitor the mosfet includes two additional terminals source and drain each connected to individual highly doped regions that are separated by the body region these regions can be either p or n type but they must both be of the same type and of opposite type to the body region the source and drain unlike the body are highly doped as signified by a sign after the type of doping if the mosfet is an n channel or nmos fet then the source and drain are n regions and the body is a p region if the mosfet is a p channel or pmos fet then the source and drain are p regions and the body is a n region the source is so named because it is the source of the charge carriers electrons for n channel holes for p channel that flow through the channel similarly the drain is where the charge carriers leave the channel the occupancy of the energy bands in a semiconductor is set by the position of the fermi level relative to the semiconductor energy band edges see also depletion region with sufficient gate voltage the valence band edge is driven far from the fermi level and holes from the body are driven away from the gate at larger gate bias still near the semiconductor surface the conduction band edge is brought close to the fermi level populating the surface with electrons in an inversion layer or n channel at the interface between the p region and the oxide this conducting channel extends between the source and the drain and current is conducted through it when a voltage is applied between the two electrodes increasing the voltage on the gate leads to a higher electron density in the inversion layer and therefore increases the current flow between the source and drain for gate voltages below the threshold value the channel is lightly populated and only a very small subthreshold leakage current can flow between the source and the drain when a negative gate source voltage positive source gate is applied it creates a p channel at the surface of the n region analogous to the n channel case but with opposite polarities of charges and voltages when a voltage less negative than the threshold value a negative voltage for the p channel is applied between gate and source the channel disappears and only a very small subthreshold current can flow between the source and the drain the device may comprise a silicon on insulator device in which a buried oxide is formed below a thin semiconductor layer if the channel region between the gate dielectric and the buried oxide region is very thin the channel is referred to as an ultrathin channel region with the source and drain regions formed on either side in or above the thin semiconductor layer other semiconductor materials may be employed when the source and drain regions are formed above the channel in whole or in part they are referred to as raised source drain regions comparison of n and p type mosfets 31 parameter nmos fet pmos fet source drain type n type p type channel type mos capacitor n type p type gate type polysilicon n p metal φ m si conduction band φ m si valence band well type p type n type threshold voltage v th positive enhancement negative depletion negative enhancement positive depletion band bending downwards upwards inversion layer carriers electrons holes substrate type p type n type modes of operation source tied to the body to ensure no body bias top left subthreshold top right ohmic mode bottom left active mode at onset of pinch off bottom right active mode well into pinch off channel length modulation evident when the switch is closed the n channel mosfet s gate raises above its threshold voltage so the mosfet then will conduct current to light the led 32 the operation of a mosfet can be separated into three different modes depending on the device s threshold voltage v th displaystyle v_ text th gate to source voltage v gs displaystyle v_ text gs and drain to source voltage v ds displaystyle v_ text ds in the following discussion a simplified algebraic model is used 33 modern mosfet characteristics are more complex than the algebraic model presented here 34 for an enhancement mode n channel mosfet the three operational modes are cutoff subthreshold and weak inversion mode criterion v gs v th displaystyle v_ text gs v_ text th according to the basic threshold model the transistor is turned off and there is no conduction between drain and source a more accurate model considers the effect of thermal energy on the fermi dirac distribution of electron energies which allow some of the more energetic electrons at the source to enter the channel and flow to the drain this results in a subthreshold current that is an exponential function of gate source voltage while the current between drain and source should ideally be zero when the transistor is being used as a turned off switch there is a weak inversion current sometimes called subthreshold leakage in weak inversion where the source is tied to bulk the current varies exponentially with v gs displaystyle v_ text gs as given approximately by 35 36 i d i d0 e v gs v th n v t displaystyle i_ text d approx i_ text d0 e frac v_ text gs v_ text th nv_ text t where i d0 displaystyle i_ text d0 is the current when v gs v th displaystyle v_ text gs v_ text th v t k t q displaystyle v_ text t kt q is the thermal voltage and n displaystyle n is the slope factor given by n 1 c dep c ox displaystyle n 1 frac c_ text dep c_ text ox where c dep displaystyle c_ text dep is the capacitance of the depletion layer and c ox displaystyle c_ text ox is the capacitance of the oxide layer this equation is generally used but is only an adequate approximation for the source tied to the bulk for the source not tied to the bulk the subthreshold equation for drain current in saturation is 37 38 i d i d0 e v g v th n v t e v s v t displaystyle i_ text d approx i_ text d0 e frac v_ text g v_ text th nv_ text t e frac v_ text s v_ text t in a long channel device there is no drain voltage dependence of the current once v ds v t displaystyle v_ text ds gg v_ text t but as channel length is reduced drain induced barrier lowering introduces drain voltage dependence that depends in a complex way upon the device geometry for example the channel doping the junction do...
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