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y the operating frequency as frequencies increase the input impedance of the mosfets decreases analog the mosfet s advantages in digital circuits do not translate into supremacy in all analog circuits the two types of circuit draw upon different features of transistor behavior digital circuits switch spending most of their time either fully on or fully off the transition from one to the other is only of concern with regards to speed and charge required analog circuits depend on operation in the transition region where small changes to v gs can modulate the output drain current the jfet and bipolar junction transistor bjt are preferred for accurate matching of adjacent devices in integrated circuits higher transconductance and certain temperature characteristics which simplify keeping performance predictable as circuit temperature varies nevertheless mosfets are widely used in many types of analog circuits because of their own advantages zero gate current high and adjustable output impedance and improved robustness vs bjts which can be permanently degraded by even lightly breaking down the emitter base vague the characteristics and performance of many analog circuits can be scaled up or down by changing the sizes length and width of the mosfets used by comparison bipolar transistors follow a different scaling law mosfets ideal characteristics regarding gate current zero and drain source offset voltage zero also make them nearly ideal switch elements and also make switched capacitor analog circuits practical in their linear region mosfets can be used as precision resistors which can have a much higher controlled resistance than bjts in high power circuits mosfets sometimes have the advantage of not suffering from thermal runaway as bjts do dubious discuss this means that complete analog circuits can be made on a silicon chip in a much smaller space and with simpler fabrication techniques mosfets are ideally suited to switch inductive loads because of tolerance to inductive kickback some ics combine analog and digital mosfet circuitry on a single mixed signal integrated circuit making the needed board space even smaller this creates a need to isolate the analog circuits from the digital circuits on a chip level leading to the use of isolation rings and silicon on insulator soi since mosfets require more space to handle a given amount of power than a bjt fabrication processes can incorporate bjts and mosfets into a single device mixed transistor devices are called bi fets bipolar fets if they contain just one bjt fet and bicmos bipolar cmos if they contain complementary bjt fets such devices have the advantages of both insulated gates and higher current density analog switches this section does not cite any sources please help improve this section by adding citations to reliable sources unsourced material may be challenged and removed september 2016 learn how and when to remove this message bidirectional analog switches pass analog signals when on or block them by presenting a high impedance when off the mosfets used are typically symmetrical such that their drain and source exchange places depending on the relative voltages of their electrodes at any moment the source would be the more negative side for an nmos or the more positive side for a pmos all of these switches are limited on what signals they can pass or stop by their gate source gate drain and source drain voltages exceeding the voltage current or power limits will potentially damage the switch see power mosfet subsection down below single type this analog switch uses a four terminal symmetrical mosfet of either p or n type in the case of an n type switch the body is connected to the most negative supply usually gnd and the gate is used as the switch control whenever the gate voltage exceeds the source voltage by at least a threshold voltage the mosfet conducts the higher the voltage the more the mosfet can conduct an nmos switch passes all voltages less than v gate v threshold_nmos but passes lower voltages better than higher ones when the switch is conducting it typically operates in the linear or ohmic mode of operation since the source and drain voltages will typically be nearly equal in the case of a pmos the body is connected to the most positive voltage and the gate is brought to a lower potential to turn the switch on the pmos switch passes all voltages higher than v gate v threshold_pmos note enhancement mode pmos fets have a negative threshold voltage but passes higher voltages better than lower ones dual type cmos main article transmission gate electronic switch the cmos analog switch passes the signal through both a pmos qp and an nmos qn when st is high the switch provides a low resistance between ua and ub either of which could be considered the input or output this complementary or cmos type of switch uses one pmos and one nmos fet connected in parallel to counteract the limitations of the single type switch 61 when used in digital logic it is called a transmission gate the fets have their drains and sources connected in parallel the body of the pmos is connected to the high potential vpos in diagram and the body of the nmos is connected to the low potential vneg to turn the switch on the gate of the pmos is driven to the low potential and the gate of the nmos is driven to the high potential for voltages between vpos v threshold_nmos and vneg v threshold_pmos both fets conduct the signal though with the nmos passing lower voltages better while the pmos passes higher voltages better for voltages less than vneg v threshold_pmos the nmos conducts alone for voltages greater than vpos v threshold_nmos the pmos conducts alone the voltage limits for this switch are the gate source gate drain and source drain voltage limits for both fets also the pmos is typically two to three times wider than the nmos so the switch will be balanced for speed in the two directions tri state circuitry sometimes incorporates a cmos mosfet switch on its output to provide for a low ohmic full range output when on and a high ohmic mid level signal when off construction gate material the primary criterion for the gate material is that it is a good conductor highly doped polycrystalline silicon is an acceptable but certainly not ideal conductor and also suffers from some more technical deficiencies in its role as the standard gate material nevertheless there are several reasons favoring use of polysilicon the threshold voltage and consequently the drain to source on current is modified by the work function difference between the gate material and channel material because polysilicon is a semiconductor its work function can be modulated by adjusting the type and level of doping furthermore because polysilicon has the same bandgap as the underlying silicon channel it is quite straightforward to tune the work function to achieve low threshold voltages for both nmos and pmos devices by contrast the work functions of metals are not easily modulated so tuning the work function to obtain low threshold voltages lvt becomes a significant challenge additionally obtaining low threshold devices on both pmos and nmos devices sometimes requires the use of different metals for each device type the silicon sio 2 interface has been well studied and is known to have relatively few defects by contrast many metal insulator interfaces contain significant levels of defects which can lead to fermi level pinning charging or other phenomena that ultimately degrade device performance in the mosfet ic fabrication process it is preferable to deposit the gate material prior to certain high temperature steps in order to make better performing transistors such high temperature steps would melt some metals limiting the types of metal that can be used in a metal gate based process while polysilicon gates have been the de facto standard for the last twenty years they do have some disadvantages which have led to their likely future replacement by metal gates these disadvantages include polysilicon is not a great conductor approximately 1000 times more resistive than metals which reduces the signal propagation speed through the material the resistivity can be lowered by increasing the level of doping but even highly doped polysilicon is not as conductive as most metals to improve conductivity further sometimes a high temperature metal such as tungsten titanium cobalt and more recently nickel is alloyed with the top layers of the polysilicon such a blended material is called silicide the silicide polysilicon combination has better electrical properties than polysilicon alone and still does not melt in subsequent processing also the threshold voltage is not significantly higher than with polysilicon alone because the silicide material is not near the channel the process in which silicide is formed on both the gate electrode and the source and drain regions is sometimes called salicide self aligned silicide when the transistors are extremely scaled down it is necessary to make the gate dielectric layer very thin around 1 nm in state of the art technologies a phenomenon observed here is the so called poly depletion where a depletion layer is formed in the gate polysilicon layer next to the gate dielectric when the transistor is in the inversion to avoid this problem a metal gate is desired a variety of metal gates such as tantalum tungsten tantalum nitride and titanium nitride are used usually in conjunction with high κ dielectrics an alternative is to use fully silicided polysilicon gates a process known as fusi present high performance cpus use metal gate technology together with high κ dielectrics a combination known as high κ metal gate hkmg the disadvantages of metal gates are overcome by a few techniques 62 the threshold voltage is tuned by including a thin work function metal layer between the high κ dielectric and the main metal this layer is thin enough that the total work function of the gate is influenced by both the main metal and thin metal work functions either due to alloying during annealing or simply due to the incomplete screening by the thin metal the threshold voltage thus can be tuned by the thickness of the thin metal layer high κ dielectrics are now well studied and their defects are understood hkmg processes exist that do not require the metals to experience high temperature anneals other processes select metals that can survive the annealing step insulator as devices are made smaller insulating layers are made thinner often through steps of thermal oxidation or localised oxidation of silicon locos for nano scaled devices at some point tunneling of carriers through the insulator from the channel to the gate electrode takes place to reduce the resulting leakage current the insulator can be made thinner by choosing a material with a higher dielectric constant to see how thickness and dielectric constant are related note that gauss s law connects field to charge as q κ ϵ 0 e displaystyle q kappa epsilon _ 0 e with q charge density κ dielectric constant ε 0 permittivity of empty space and e electric field from this law it appears the same charge can be maintained in the channel at a lower field provided κ is increased the voltage on the gate is given by v g v ch e t ins v ch q t ins κ ϵ 0 displaystyle v_ text g v_ text ch e t_ text ins v_ text ch frac qt_ text ins kappa epsilon _ 0 with v g gate voltage v ch voltage at channel side of insulator and t ins insulator thickness this equation shows the gate voltage will not increase when the insulator thickness increases provided κ increases to keep t ins κ constant see the article on high κ dielectrics for more detail and the section in this article on gate oxide leakage the insulator in a mosfet is a dielectric which can in any event be silicon oxide formed by locos but many other dielectric materials are employed the generic term for the dielectric is gate dielectric since the dielectric lies directly below the gate electrode and above the channel of the mosfet junction design the source to body and drain to body junctions are the object of much attention because of three major factors their design affects the current voltage i v characteristics of the device lowering output resistance and also the speed of the device through the loading effect of the junction capacitances and finally the component of stand by power dissipation due to junction leakage mosfet showing shallow junction extensions raised source and drain and halo implant raised source and drain are separated from gate by oxide spacers the drain induced barrier lowering of the threshold voltage and channel length modulation effects upon i v curves are reduced by using shallow junction extensions in addition halo doping can be used that is the addition of very thin heavily doped regions of the same doping type as the body tight against the junction walls to limit the extent of depletion regions 63 the capacitive effects are limited by using raised source and drain geometries that make most of the contact area border thick dielectric instead of silicon 64 these various features of junction design are shown with artistic license in the figure scaling this section is written like a personal reflection personal essay or argumentative essay that states a wikipedia editor s personal feelings or presents an original argument about a topic please help improve it by rewriting it in an encyclopedic style september 2016 learn how and when to remove this message further information dennard scaling trend of intel cpu transistor gate length mosfet version of gain boosted current mirror m 1 and m 2 are in active mode while m 3 and m 4 are in ohmic mode and act like resistors the operational amplifier provides feedback that maintains a high output resistance over the past decades the mosfet as used for digital logic has continually been scaled down in size typical mosfet channel lengths were once several micrometres but modern integrated circuits are incorporating mosfets with channel lengths of tens of nanometers robert dennard s work on scaling theory was pivotal in recognising that this ongoing reduction was possible intel began production of a process featuring a 32 nm feature size with the channel being even shorter in late 2009 the semiconductor industry maintains a roadmap the itrs 65 which sets the pace for mosfet development historically the difficulties with decreasing the size of the mosfet have been associated with the semiconductor device fabrication process the need to use very low voltages and with poorer electrical performance necessitating circuit redesign and innovation small mosfets exhibit higher leakage currents and lower output resistance smaller mosfets are desirable for several reasons the main reason to make transistors smaller is to pack more and more devices in a given chip area this results in a chip with the same functionality in a smaller area or chips with more funct...
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